The present invention relates generally to semiconductor device processing and, more particularly, to a method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten (TiW) seed layer.
In the manufacture of semiconductor devices, a selective plating process has been developed in order to plate copper, nickel, gold and other conductive metals on coils, vias, pads and other interconnect structures. In this selective plating process, electrical current is conducted through a layer of refractory metal (e.g., tantalum/tantalum nitride (Ta/TaN)) to plate metal on lines or pads using copper seed. The plating conditions are specifically designed so as to enable deposition on pre-patterned copper pads only, not on the Ta/TaN seed. Because there is no photoresist used during the plating process, any over-plating otherwise caused by delamination of photoresist and bath contamination due to photoresist leaching is eliminated. Moreover, through the use of nickel/gold plating, the sidewalls of the copper seed are completely covered with the nickel/gold, thereby providing excellent corrosion resistance with this “self-encapsulated” metallurgy and eliminating the need for an extra passivation layer.
In addition, the use of selective copper plating can afford the opportunity for reduced chemical-mechanical polishing (CMP) time since less “extraneous” copper is formed from the plating. Pads with nickel and gold may be used either for wirebonding with thicker gold or for lead-free solder paste screening as capture pads with a flash of gold. The gold on the capture pad is demonstrated to exhibit very low contact resistance, which is ideal for electrical testing before C4 bumping. Furthermore, the electroplated nickel and gold as terminal metals has demonstrated promising results in stress tests. More specifically, it has opened up tremendous opportunities for pitch reduction, as well as a more protective surface for low-k di-electrics underneath at a lower test force and better reliability performance. After the completion of the metal plating, the Ta/TaN seed layer is removed by either a reactive ion etch process or a CMP process.
However, conventional selective plating processes are not without their own disadvantages. First, there is a thickness uniformity issue associated with using a Ta/TaN seed layer. A Ta/TaN seed layer at 800 Angstroms (Å) is considered very resistive. In the case of copper plating, the edge areas can be plated to a thickness about twice that of the center areas, which is not acceptable for applications where copper uniformity is critical. Second, the presence of surface topography (e.g., corners or other defects) in the seed layer can dramatically increase local plating currents. In certain cases, these local currents can be too high and thus start to plate metal on the Ta/TaN seed. In turn, the over-plated metal nodules can short the electrical features of the device. Accordingly, the applied plating current density is kept fairly low, which results in longer plating times, as well as possibly changing the film microstructure and properties.
Still another disadvantage of conventional selective plating results from the Ta/TaN removal process (i.e., reactive ion etching). A reactive ion etch (RIE) process has the effect of removing some gold from the surface. Although the loss of gold can be compensated for, the redeposition of gold on the manufacturing tool presents a manufacturing concern. On the other hand, a resulting thinner gold layer can lead to wire bond failures. CMP is also not a desirable method for Ta/TaN seed removal, due to the topographic features of the structure. A third possibility is a wet chemical etch to remove the Ta/TaN seed, however the etchant materials are difficult to handle from a manufacturing standpoint.
Accordingly, it would be desirable to implement a selective plating process that also allows for higher conductivity and tool throughput, and without the disadvantages as mentioned above.